1. Field of the Invention
The present invention relates to a semiconductor memory device and a control method of the semiconductor memory device, which are applied to, for instance, a NAND flash memory.
2. Description of the Related Art
In recent years, a demand for nonvolatile memories has been increasing in accordance with an increase in memory capacity thereof. A NAND flash memory is an example of such nonvolatile memories (see, e.g. Jpn. Pat. Appln. KOKAI Publication No. 2004-14043).
It is known, however, that in the memory cells of the NAND flash memory, if write/erase operations for data rewrite are repeated, the characteristics of the memory cells vary and, as a result, the speed of the erase operation becomes lower and the speed of the write operation becomes higher.
For example, at the time of the erase operation, an erase voltage Vera is gradually stepped up, and a plurality of pulses are applied until the erase voltage Vera reaches a target threshold voltage. However, there is a limit to the erase voltage Vera that is to be applied and the number of pulses. Consequently, if the characteristics have varied and the speed of the erase operation has decreased, the threshold voltages of the memory cells do not reach even if the erase voltage Vera reaches its upper limit, and there occurs an erase defect in which the erase operation is not completed.
In addition, the memory cell in which the erase defect has occurred becomes a defective element. Hence, if the number of times of rewrite increases, erase defects occur and the number of defective elements increases.